Jake Hafele - Project Portfolio
FPGA Intro (Click here for more info)
The last time I had written any Verilog was when I worked as a Digital Logic Teaching Assistant back in the Spring 2021 semester of school. Since then, I have done a lot of work on Iowa State’s solar car team, PrISUm, learning many skills related to PCB design and system wide testing. As I look ahead towards getting my Masters at Iowa State, I have thought about learning more about FPGA’s since I enjoyed my time in Digital Logic learning about combinational logic, sequential logic, and state machines.

  To get myself more familiar with the basics of digital design and Verilog, I decided to buy the Basys 3 Artix 7 FPGA development board sold by Diligent. This board comes with a 100 MHz clock, 16 switches, 16 LED’s, 5 buttons, a USB Host, UART Bridge, VGA output, and seven segment displays. Between all of these features, I figured that I would be able to apply what I have learned in my digital logic class and go beyond it to more topics based on my personal interests and future classes.

  On this specific page, both videos cover demos and conversation about my time working with designing modules and testbenches related to combination logic, sequential logic, finite state machines, UART communication, and PS2 keyboard receiving interfaces. As a guide, I have been following through the first 9 chapters of the textbook “FPGA Prototyping by Verilog Examples” by Pong P. Chu. This book has helped expand on the syntax that is both synthesizable and not for Verilog, while also explaining useful design practices. I have found this extremely beneficial for modules involving UART, PS2 communication, and complex state machines. Normally in each chapter, the concepts and basic outline of a module will be defined, with extra experiments added at the bottom to expand upon what is given. Through my work over two months, the code presented in these demos are from those experiments. If you are interested in the modules and testbenches I have designed, feel free to access my GitHub repository below!

Senior Design: Digital ASIC Fabrication
During the Spring 2023 Semester, I began my senior design project at Iowa State University. Senior Design is a two-semester course, with a focus on research and planning in the first semester, and then design and implementation in the second semester. The project that I chose to join with three other group members was Digital ASIC Fabrication, which involves designing and fabricating a digital ASIC. Our client and advisor are Dr. Duwe, a professor at Iowa State who researches and teaches about computer architecture and cyber security topics. Dr. Duwe has had two previous senior design groups follow the same process and design cycle as we are, each staggered one semester apart. The first senior design team was able to successfully get their chip approved and fabricated, and we are currently waiting to receive it. For our project, our requirements are to design a digital ASIC chip using Verilog and open-source tools, alongside developing firmware and a bring-up plan to assist a future team in verifying the functional requirements of our design.

  We are able to create our digital ASIC by working through the company eFabless, which is sponsored by Google. The goal of eFabless is to use open-source tools that are freely available to silicon prove both digital and analog ASICs for hobbyists, researchers, and students, who do not have a large pool of resources to take advantage of. Being a senior design team, this was an excellent opportunity to learn more about writing Verilog, using new open-source tools, and designing a chip for fabrication that would come back on an SOC development board. All of the submitted designs are required to be open-source, with the benefit of receiving 5 ASICs that are placed on a development board. eFabless produces their silicon wafers through the U.S. based foundry SkyWater, which takes advantage of 130 nm technology and a standard cell library to fabricate our project. Due to this, we are limited to this fabrication process and the standard cell library that is provided by SkyWater in their 130 nm product development kit. Each project submission is produced on a wafer that houses open-source designs from multiple different projects, enabling eFabless to produce small amounts of ASICs for each team at a reduced cost. While working with open-source tools and a limited production cycle has been difficult through eFabless, they are in a very unique and rare position by offering free digital ASIC fabrication, that is returned on an integrated development SOC board for us to test.

  As of December 2023, the project has been completed, and has passed the precheck so that it is ready for submission in the next Multi Project Wafer submission at the Skywater foundry with the 130nm process and open-source PDK. I learned a lot about this process both from utilizing rapidly evolving open-source tools, and working on varying parts of the ASIC design process, such as functional design, verification, and place and route all at different times! This project was extremely valuable and was a great capstone for my senior year of school at Iowa State University.

Documentation

Useful Links

MIPS Proccessor
During the Spring 2023 school semester, I took my first Computer Architecture class, CprE 381, at Iowa State University. In this class, we learned how to convert basic programs into assembly, design and analyze a MIPS processor, and compare different cache designs. In the lab portion of the class, we focused on implementing three different MIPS processors using VHDL and ModelSim, including a single cycle, 5 stage software pipeline, and 5 stage hardware pipeline processor. We started with the single cycle processor, and designed modules to increment the program counter, decode instructions, a register file, a sign extender, and an ALU. For the 5 stage processors, we broke apart each of these components into five separate stages, so that we could reduce the critical path latency and improve the maximum clock rate of our design. Near the end of the project, me and my partner had about a month of time left. Due to this, we decided to work on an extra credit project through the form of an FPGA wrapper with the Altera DE2 FPGA Development board. For more information on each of these designs, please look at the other tabs for this project.

  The goal of this project was to learn more about implementing specific components of a processor, and analyzing the performance tradeoffs between each of our three processors. For the software pipeline, we inserted NOP instructions to remove the risk of data and control dependencies within our pipeline. This led to an increased number of instructions, which made our overall execution time larger. As we implemented stalling in the pipeline registers of our hardware pipeline, we were able to reduce the number of instructions used, with the tradeoff of our CPI increasing from a near average of 1. After adding forwarding we were able to reduce the average CPI of our hardware pipeline while retaining a faster maximum clock frequency compared to our single cycle design. By analyzing these choices, we were able to make educated design decisions on how to improve our HW pipeline design, and yield an improved performance compared to our first two processor designs.

  Another goal of the project was to take ownership in our required work by taking it a step further with an extra credit project. As mentioned before, we had extra time near the end of the semester, so me and my partner Thomas worked on designing an FPGA wrapper for the Altera DE2 FPGA development board. With this, we were able to combine Verilog code from our previous digital design class, that I also was a teaching assistant for, and a mix of FPGA modules, from the previous library I designed, to make a robust wrapper. It was very satisfying to combine designs for clock dividers, button debouncers, and seven segment display interfaces that had already been extensively tested, and apply them to an interesting and challenging MIPS processor design. This was also a fantastic goal and achievement since we were finally able to see our processor run on real hardware, and not just the required simulations for the course and lab. For more information, please reference the FPGA tab on this page.

Design Reports

Controls Spreadsheets
FPGA OLED Controller
Over the Summer of 2023, I was looking for a project that could help me practice reading datasheets, implement more complex state machines, and provide a useful module to help me take advantage of other FPGA projects. After spending some time thinking of ideas, I landed on using Digilent’s 96x64 OLEDrgb display PMOD. This display uses the SSD1331 OLED controller, and the PMOD is wired to be used as a write only SPI interface.

  To utilize this PMOD, my goal was to create an array of 8x8 pixel ASCII characters, that could be stored or updated as ASCII values. This could be converted from binary, hex, bcd, or scanned through something like UART. It would be very straightforward to convert the values into ASCII, as long as I could keep that ASCII array as a top level input and treat the OLED controller as a hands off display after it is tested. I would also like to be able to use inputs to change the color of the text and background, to make the displays more dynamic based on different states of the logic modules it works with.

  As of now, the first semester of senior design has been completed. During this time, we were able to determine our design plan with doctor Duwe, research more about the tools we will be using, and begin testing submodules in our design. Our team decided on a modular design with multiple different functions, including a clock gating module, digital signals processing filter, an external SPI interface, and more. The intent of choosing a modular design was to push the capabilities of the fabrication process at the SkyWater foundry, and see how many working pieces we could receive on our digital ASIC through working with eFabless.

The following requirements are to be followed to interface with the OLED controller:


  The above requirements are determined based on the reference manual for the SSD1331 OLED display controller and the schematic for the OLEDrgb breakout PMOD from Digilent. This would dictate the turn on sequence for the OLED controller, and lead me to designing a standard write only SPI module, which would handle driving the CS and MOSI pins.

The following requirements were determined by myself to achieve the goal of a fully controllable ASCII display:


The following set of modules were planned to be implemented, to achieve a fully customizable ASCII display in real time:


References


Documentation